The UVLO pin serves as the master enable or disable pin. To use the UVLO pin to program undervoltage lockout control for the HV-port, LV-port, or VCC rail, see Section 8.5.2 for details.

There are two UVLO voltage thresholds. When the pin voltage is externally pulled below 1.25 V, the LM5170-Q1 is in shutdown mode, in which all gate drivers are in the OFF state, all internal logic resets, the VINX pin is disconnected from VIN pin, and the IC draws less than 20 µA through the VIN, VCC and VCCA pins.

When the VCC voltage is above the 8.5 V and the UVLO pin voltage is pulled higher than 1.5 V but lower than 2.5 V, the LM5170-Q1 is in the initialization mode in which the nFAULT pin is pulled up to approximately 5 V, but the rest of the LM5170-Q1 remain off.

When the UVLO pin is pulled higher than 2.5 V, which is the UVLO release threshold and the master enable threshold, the LM5170-Q1 starts the MOSFET failure detection in a period of 2 to 3 ms (see Section 8.3.16). If no failure is detected, BRKG pin starts to source a 330-µA current to charge the gates of the breaker MOSFETs.

When the BRKG to BRKS voltage is above 8.5 V, the LM5170-Q1 enters standby mode. In standby mode, the VINX pin is internally connected to the VIN pin through an internal cutoff switch (see Figure 8-2), and the internal 1-MΩ OVPB pullup resistor is connected to the CSB1 pin through another internal cutoff switch (see Figure 8-18). The oscillator and the RAMP1 and RAMP2 generators start to operate, and the SYNCOUT pin starts to send clock pulses at the oscillator frequency, and the LM5170-Q1 is ready to operate. The LO1, LO2, HO1, and HO2 drivers remain off until the EN1, EN2, and DIR inputs command them to operate.

When a MOSFET gate-to-source short-circuit failure is detected, the LM5170-Q1 is latched off. The latch can only be reset by pulling the VCC pin below 8 V, or by pulling the UVLO pin below 1.25 V. For details, see Section 8.3.16.