The LM5170-Q1 oscillator frequency is set by the external resistor R_OSC connected between the OSC pin and AGND, as shown in Figure 8-13. The OSC pin must never be left open whether or not an external clock is present. To set a desired oscillator frequency F_OSC, R_OSC is approximately determined by Equation 17:

Equation 17.

R_OSC must be placed as close as possible to the OSC and AGND pins. Take the tolerance of the external resistor and the frequency tolerance indicated in Section 7.5 into account when determining the worst case operating frequency.

The LM5170-Q1 also includes a Phase-Locked Loop (PLL) circuit to manage multiphase interleaving phase angle as well as the synchronization to the external clock applied at the SYNCIN pin. When no external clock is present, the converter operates at the oscillator frequency given by Equation 17. If an external clock signal of a frequency within ± 20% of F_SW is applied (see Section 8.3.14), the converter will switch at the frequency of the external clock F_{EX_CLK}, namely Equation 18:

Equation 18.

Two internal clock signals CLK1 and CLK2 are produced to control the interleaving operation of CH-1 and CH-2, respectively. The third clock signal is output at the SYNCOUT pin. All these three clock signals run at the same frequency of F_SW. The phase angles among these three clock signals are controlled by the state of the OPT pin. See Section 8.4.1 for details.

Figure 8-13 Oscillator and Interleaving Clock Programming