Careful PCB layout is critical to achieve low EMI and stable power supply operation as well as optimal efficiency. Make the high frequency current loops as small as possible, and follow these guidelines of good layout practices:

1. For high power board design, use at least a 4-layer PCB of 2-oz or thicker copper planes. Make the first inner layer a ground plane that is adjacent to the top layer on which the power components are installed, and use the second inner layer for the critical control signals including the current sense, gate drive, commands, and so forth. The ground plane between the signal and top layers helps shield switching noises on the top layer away from affecting the control signals.
2. Optimize the component placements and orientations before routing any traces. Place the power components such that the power flow from port to port is direct, straight and short. Avoid making the power flow path zigzag on the board.
3. Identify the high frequency AC current loops. In the bidirectional converter, the AC current loop of each channel is along the path of the HV-port rail capacitors, high-side MOSFET, low-side MOSFET, and back to the HV-port rail capacitors’ return. Place these components such that the current flow path is short, direct and the special area enclosed by the loop is minimized.
4. Place the power circuit symmetrically between CH-1 and CH-2. Split the HV-port rail capacitors and LV-port rail capacitors evenly between CH-1 and CH-2.
5. If more than one LM5170-Q1 is used on the same PCB for multi phases, place the circuits of each LM5170-Q1 in the similar pattern.
6. Use adequate copper for the power circuit, so as to minimize the conductions losses on high-current PCB tracks. Adequate copper can also help dissipate the heat generated by the power components, especially the power inductors, power MOSFETs, and current sense resistors. However, pay attention to the polygon of the switch node, which connects the high-side MOSFET source, low-side MOSFET drain, power inductor, and the controller SW pin. The switch node polygon sees high dv/dt during switching operation. To minimize the EMI emission by the switch node polygon, make its size sufficient but not excessive to conduct the switched current.
7. Use appropriate number of via holes to conduct current to, and heat through, the inner layers.
8. Always separate the power ground from the analog ground, and make a single point connection of the power ground, analog ground, and the EP pad, at the location of the PGND pin.
9. Minimize current-sensing errors by routing each pair of CSA and CSB traces using a kelvin-sensing directly across the current sense resistors. The pair of traces must be routed closely side by side for good noise immunity.
10. Route sensitive analog signals of the CS, IOUT, COMP, OVPA, and OVPB pins away from the high-speed switching nodes (HB, HO, LO, and SW).
11. Route the paired gate drive traces, namely the pairs of HO1 and SW1, HO2 and SW2, LO1 and return, and LO2 and return, closely side by side. Route CH-1 gate drive traces in symmetry with CH-2’s.
12. Place the IC setting, programming and controlling components as close as possible to the corresponding pins, including the following component: R_OSC, R_DT, R_IPK, C_RAMP1, C_RAMP2, R_OVPA, R_OVPB, C_ISETA, C_COMP1, R_COMP2, C_COMP1, C_COPM2, C_HF1, and C_HF2.
13. Place the bypass capacitors as close as possible to the corresponding pins, including C_VIN, C_VCC, C_VCCA, C_HB1, C_HB2, C_OPVA, C_OVPB, as well as the 100-pF current sense common-mode bypassing capacitors.
14. Flood each layer with copper to take up the empty areas for optimal thermal performance.
15. Apply heat sink to components as necessary according to the system requirements.