5 Pin Configuration and Functions

Figure 5-1 HTSSOP-28PWP PackageTop View

Table 5-1 Pin Functions

PIN		DESCRIPTION
NAME	HTSSOP	DESCRIPTION
EN/UVLO	1	Enable pin. For EN/UVLO < 0.4 V, the LM5176-Q1 is in a low current shutdown mode. For EN/UVLO > 1.22 V, the PWM function is enabled, provided VCC exceeds the VCC UV threshold.
VIN	2	The input supply pin to the IC. Connect V_IN to a supply voltage between 4.2 V and 55 V.
VISNS	3	V_IN sense input. Connect to power stage input rail.
MODE	4	1.38 V < MODE < 2.22 V : CCM, Hiccup Enabled	(Set R_MODE resistor to AGND = 93.1 kΩ)
MODE	4	2.6 V < MODE < VCC: CCM, Hiccup Disabled	(Set R_MODE resistor to AGND = 200 kΩ or connect to VCC)
DITH	5	A capacitor connected between the DITH pin and AGND is charged and discharged with a current source. As the voltage on the DITH pin ramps up and down, the oscillator frequency is modulated by 10% of the nominal frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is ignored.
RT/SYNC	6	Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock.
SLOPE	7	A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable current mode operation in both buck and boost mode.
SS	8	Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.
COMP	9	Output of the error amplifier. An external RC network connected between COMP and AGND compensates the regulator feedback loop.
AGND	10	Analog ground of the IC
FB	11	Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin.
VOSNS	12	V_OUT sense input. Connect to the power stage output rail.
ISNS(–) ISNS(+)	13 14	Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between ISNS(+) and ISNS(–) can be located either on the input side or on the output side of the converter. If the sensed voltage across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC) control loop becomes active and starts discharging the soft-start capacitor to regulate the drop across ISNS(+) and ISNS(-) to 50 mV. Short ISNS(+) and ISNS(-) together to disable this feature.
CSG	15	The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side (ground) of the current sense resistor.
CS	16	The positive input to the PWM current sense amplifier
PGOOD	17	Power-Good open-drain output. PGOOD is pulled low when FB is outside a -9%/+10% regulation window around the 0.8-V V_REF.
SW2 SW1	18 28	The boost and the buck side switching nodes respectively.
HDRV2 HDRV1	19 27	Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs.
BOOT2 BOOT1	20 26	An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins respectively to provide bias to the high-side MOSFET gate drivers.
LDRV2 LDRV1	21 25	Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs.
PGND	22	Power ground of the IC. The high current ground connection to the low-side gate drivers.
VCC	23	Output of the VCC bias regulator. Connect capacitor to ground.
BIAS	24	Optional input to the VCC bias regulator. Powering VCC from an external supply instead of V_IN can reduce power loss at high V_IN. For V_BIAS > 8 V, the VCC regulator draws power from the BIAS pin.
PowerPAD™	-	The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a PCB ground plane for improved power dissipation.