ZHCSTC5B October 2023 – June 2024 LM51772
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Buck-Boost Control Scheme
- 7.3.2 Power Save Mode
- 7.3.3 Programmable Conduction Mode PCM
- 7.3.4 Reference System
- 7.3.5 Supply Voltage Selection – VSMART Switch and Selection Logic
- 7.3.6 Enable and Undervoltage Lockout
- 7.3.7 Internal VCC Regulators
- 7.3.8 Error Amplifier and Control
- 7.3.9 Output Voltage Discharge
- 7.3.10 Peak Current Sensor
- 7.3.11 Short Circuit - Hiccup Protection
- 7.3.12 Current Monitor/Limiter
- 7.3.13 Oscillator Frequency Selection
- 7.3.14 Frequency Synchronization
- 7.3.15 Output Voltage Tracking
- 7.3.16 Slope Compensation
- 7.3.17 Configurable Soft Start
- 7.3.18 Drive Pin
- 7.3.19 Dual Random Spread Spectrum – DRSS
- 7.3.20 Gate Driver
- 7.3.21 Cable Drop Compensation (CDC)
- 7.3.22 CFG-pin and R2D Interface
- 7.3.23 Advanced Monitoring Features
- 7.3.24
Protection Features
- 7.3.24.1 Thermal Shutdown (TSD)
- 7.3.24.2 Over Current Protection
- 7.3.24.3 Output Over Voltage Protection 1 (OVP1)
- 7.3.24.4 Output Over Voltage Protection 2 (OVP2)
- 7.3.24.5 Input Voltage Protection (IVP)
- 7.3.24.6 Input Voltage Regulation (IVR)
- 7.3.24.7 Power Good
- 7.3.24.8 Boot-Strap Under Voltage Protection
- 7.3.24.9 Boot-strap Over Voltage Clamp
- 7.3.24.10 CRC - CHECK
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 LM51772 Registers
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Custom Design with WEBENCH Tools
- 9.2.2.2 Frequency
- 9.2.2.3 Feedback Divider
- 9.2.2.4 Inductor and Current Sense Resistor Selection
- 9.2.2.5 Output Capacitor
- 9.2.2.6 Input Capacitor
- 9.2.2.7 Slope Compensation
- 9.2.2.8 UVLO Divider
- 9.2.2.9 Soft-Start Capacitor
- 9.2.2.10 MOSFETs QH1 and QL1
- 9.2.2.11 MOSFETs QH2 and QL2
- 9.2.2.12 Loop Compensation
- 9.2.2.13 External Component Selection
- 9.2.3 Application Curves
- 9.3 Power Supply Recommendations
- 9.4 Layout
- 9.5 USB-PD Source with Power Path
- 9.6 Parallel (Multiphase) Operation
- 9.7 Constant Current LED Driver
- 9.8 Wireless Charging Supply
- 9.9 Bi-Directional Power Backup
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.3.3 Programmable Conduction Mode PCM
The device also features a power save technique for high current applications. The main drawback of in most of the fixed frequency buck-boost operations are the power losses of the 4 active switches during the buck-boost mode. The Programmable Conduction Mode (PCM) is forcing the converter PWM logic to stop the switching operation in a programmable input voltage window. This function is available after the soft-start of the converter stage finishes. If the input voltage is inside the PCM window the output voltage approximately equals the input voltage as both high side FETs (Q1, Q4) are connecting the input to the output via the external power stage. Outside the programmed VI window the selected thresholds are representing the nominal regulation targets of the converter.
The FETs supply are maintained by the integrated charge pump circuit of the device. During the PCM the current limit for the peak current protection is fully operational and the user benefits from a cycle-by-cycle current limit. The SCP hiccup protection can be used to overcome excessive thermal heating during a short like in the normal operation.
The integrated charge pump will operate down to the min. recommended PCM voltage. It is not recommended to program the PCM threshold below this value.
For low output currents and load profiles that have light load conditions the MODE pin can be used to further reduce the power consumption during the PCM is active. If the MODE pin is low the PCM deactivates the internal bias circuits to reduce the power consumption by monitoring the low inductor current.
The two voltage thresholds for this window are customer programmable via the I2C interface in register Table 8-19. A pre-selected thershold for the PCM can be enabled via the R2D pin (see:Table 7-5 ).
Figure 7-11 Output Voltage vs. Input Voltage
If you using the I2C interface of the device the upper threshold is set by the VOUT_TARGET1 logical register. The lower threshold is given by the hysteresis referenced to the Vo target and the selected hysteresis value set by the PCM_WINDOW_LOW register field.
If the thresholds are set by the external feedback divider the upper threshold of the PSM voltage window given by the FB-PIN and is equal to the nominal output voltage if the PCM is disabled. The lower threshold is programmed by default setting of the PCM_WINDOW_LOW register field and can be enabled/disabled via the CFG-PIN (PCM_EN). In case of using the ext. FB and R2D the VIN-FB-pin need to be connected to the input voltage using the same divider ration as the divider placed for Vo and connected to the FB-pin.
The OVP1 and power good thresholds of the protection features are fully functional if PCM is enabled and the input voltage outside the programmed window i.e. the convert regulates active to one of the two thresholds.