With the MODE pin low, power save mode (PSM) is active. In this operating mode, the switching activity is reduced and efficiency is maximized. If the mode pin is high, power save mode is disabled. The converter then operates operates in continuous conduction mode (CCM) or forced PWM mode (fPWM).

In PFM boost, buck or in buck-boost mode, the converter is operating down to the minimum defined peak current. If this minimum current (PSM entry threshold) is reached the PWM changes the operation to single pulse. The single pulse operation consists all three states (I, II.III). The duty cycles in single pulse operation are timer based and adopt to the different VIN and VOUT sense voltages. To get a small output voltage ripple the converter modulation scheme uses one or multiply single pulses for the switching activity below the PSM entry threshold.

If the inductor current (load current) further decreases, the frequency of the single pulses are reduced to approximately one quarter of the selected switching frequency. With a further decrease of the inductor (load current) the output voltage increases, as the energy consumed by the load is less than what the converter generates during switching. If the V_O increase the voltage regulation loop detects the increase and turns the device into a pause or if enabled (e.g Table 7-6) a TI proprietary sleep mode (uSleep).

In uSleep mode, both low sides are turned on to provide the high-side gate supply for HB1 and HB2 are charged. Other internal circuits are partially turned off to reduce the current consumption of the converter to a minimum possible. In case the output voltage reaches the nominal output voltage set point, the switching activity starts again after a short wake-up time.

Figure 7-6 Timing Diagram for the Power Save Mode (uSleep Disabled)

Figure 7-7 Timing Diagram for the Power Save Mode (uSleep Enabled)

The PSM - ACM (automated conduction mode) is a high output current power save mode for the 4 switch buck-boost operation. In the buck-boost operation area with loads higher than the PSM entry threshold, switching pulses are skipped and the control enters ACM. Here the device regulation maintains in State II and conducts the input to the output of the power stage. When necessary, the control initiates switching activities with a minimum time of state I or state III to maintain the inductor current as required by the voltage regulation loop. Hence the output voltage is still fully regulated and the device maintains all protection features like the OCP.

Figure 7-9 Functional State Diagram for the PSM with default register settings

The LM51772 features an adaptive power save mode threshold (see Generic graph of PSM entry threshold and ripple current versus input voltage ). The internal algorithm derives I_VT(PSM) from:

• The applied input voltage sense on VIN pin
• The output voltage derived from the VOUT pin
• The selected or programmed slope compensation factor (m_sc) via the ADDR/SLOPE pin (Table 7-4) or SEL_SLOPE_COMP register in Table 8-17
• The selected inductor de-rating factor on the CFG3-pin (Table 7-6). The INC_INDUCTOR_DERATING increases the default setting by 1-LSB. Or the programmed SEL_INDUCT_DERATE register in Table 8-17. The inductor de-rating should be selected based on the inductor manufacturer data sheet at the maximum current the power stage(R_CS) of the LM51772 is designed for.

Figure 7-10 Generic graph of PSM entry threshold and ripple current versus input voltage

If the converter operates in Buck operation with on-times smaller than ≈300ns and light load conditions, it's recommended to turn-on the SYNC output instead of using the SYNC input function to provide low inductor current ripple.