This section presents the control loop compensation design procedure for the LM51772 buck-boost controller. The LM51772 operates mainly in buck or boost modes, separated by a transition region, and therefore, the control loop design is done for both buck and boost operating modes. Then, a final selection of compensation is made based on the mode that is more restrictive from a loop stability point of view. Typically, for a converter designed to go deep into both buck and boost operating regions, the boost compensation design is more restrictive due to the presence of a right half plane zero (RHPZ) in boost mode.

The boost power stage output pole location is given by:

where

• R_OUT = 5.0Ω corresponds to the maximum load of 5.0A.

The boost power stage ESR zero location is given by:

The boost power stage RHP zero location is given by:

where

• D_MAX is the maximum duty cycle at the minimum V_IN.

The buck power stage output pole location is given by:

The buck power stage ESR zero location is the same as the boost power stage ESR zero.

It is clear from Equation 59 that RHP zero is the main factor limiting the achievable bandwidth. For a robust design, the crossover frequency must be less than 1/3 of the RHP zero frequency. Given the position of the RHP zero, a reasonable target bandwidth in boost operation is around 8kHz:

For some power stages, the boost RHP zero may not be as restrictive, which happens when the boost maximum duty cycle (D_MAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by the RHP zero (f_RHP / 3) with 1/20 of the switching frequency and use the smaller of the two values as the achievable bandwidth.

The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this locates the zero at three times the buck output pole frequency, which results in approximately 30 degrees of phase loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost loop:

The compensation gain resistor, R_c1, is calculated with:

where

• D_MAX is the maximum duty cycle at the minimum V_IN in boost mode.
• A_CS is the current sense amplifier gain: 10.

The compensation capacitor, C_c1, is then calculated from:

The standard values of compensation components are selected to be R_c1 = 7.32kΩ and C_c1 = 15nF.

A high frequency pole (f_pc2) is placed using a capacitor (C_c2) in parallel with R_c1 and C_c1. Set the frequency of this pole at seven to ten times of f_bw to provide attenuation of switching ripple and noise on COMP while avoiding excessive phase loss at the crossover frequency. For a target f_pc2 = 98kHz, C_c2 is calculated using Equation 65:

Select a standard value of 270pF for C_c2. These values provide a good starting point for the compensation design. Each design must be tuned in the lab to achieve the desired balance between stability margin across the operating range and transient response time.