ZHCSMJ1 October   2021 LM61430-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EN/SYNC Uses for Enable and VIN UVLO
      2. 8.3.2  EN/SYNC Pin Uses for Synchronization
      3. 8.3.3  Clock Locking
      4. 8.3.4  Adjustable Switching Frequency
      5. 8.3.5  PGOOD Output Operation
      6. 8.3.6  Internal LDO, VCC UVLO, and BIAS Input
      7. 8.3.7  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      8. 8.3.8  Adjustable SW Node Slew Rate
      9. 8.3.9  Spread Spectrum
      10. 8.3.10 Soft Start and Recovery From Dropout
      11. 8.3.11 Output Voltage Setting
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 Auto Mode - Light-Load Operation
          1. 8.4.3.1.1 Diode Emulation
          2. 8.4.3.1.2 Frequency Reduction
        2. 8.4.3.2 FPWM Mode - Light-Load Operation
          1. 8.4.3.2.1 CCM Mode
        3. 8.4.3.3 Minimum On Time (High Input Voltage) Operation
        4. 8.4.3.4 Dropout
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  BIAS
        10. 9.2.2.10 CFF and RFF Selection
        11. 9.2.2.11 External UVLO
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息
CCM Mode

In continuous conduction mode (CCM), the LM61430-Q1 supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on-time, the SW pin voltage, VSW, swings up to approximately VIN, and the inductor current, iL, increases with a linear slope. The HS switch is turned off by the control logic as shown in Section 8.2. During the HS switch off time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. Refer to the waveforms in Figure 8-17. The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on time of the HS switch over the switching period:

Equation 5. D = TON / TSW

In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage:

Equation 6. D = VOUT / VIN
GUID-C2ED7463-3176-4104-8482-7B1CF7397642-low.gifFigure 8-17 SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)