Once a valid synchronization signal is detected, a clock locking procedure is initiated. LM61430-Q1 devices receive this signal over the EN/SYNC pin. After approximately 2048 pulses, the clock frequency changes to the frequency of the synchronization signal. Note that while the frequency is adjusted suddenly, phase is maintained so the clock cycle that lies between operation at the default frequency and at the synchronization frequency is of intermediate length. This eliminates very long or very short pulses. Once frequency is adjusted, phase is adjusted over a few tens of cycles so that rising synchronization edges correspond to rising SW node pulses. See Figure 8-4.

Figure 8-4 Synchronization Process