Start-up and shutdown are controlled by the EN/SYNC input and V_IN UVLO. For the device to remain in shutdown mode, apply a voltage below V_{EN_WAKE} (0.4 V) to the EN pin. In shutdown mode, the quiescent current drops to 0.6 µA (typical). At a voltage above V_{EN_WAKE} and below V_EN, VCC is active and the SW node is inactive. Once the EN voltage is above V_EN, the chip begins to switch normally, provided the input voltage is above 3 V.

The EN/SYNC pin cannot be left floating. The simplest way to enable the operation is to connect the EN/SYNC pin to V_IN, allowing self-start-up of the LM61435-Q1 when V_IN drives the internal VCC above its UVLO level. However, many applications benefit from the employment of an enable divider network as shown in Figure 8-1, which establishes a precision input undervoltage lockout (UVLO). This can be used for sequencing, preventing re-triggering of the device when used with long input cables, or reducing the occurrence of deep discharge of a battery power source. Note that the precision enable threshold, V_EN, has a 8.1% tolerance. Hysteresis must be enough to prevent re-triggering. External logic output of another IC can also be used to drive the EN/SYNC pin, allowing system power sequencing.

Figure 8-1 VIN UVLO Using the EN pin

Resistor values can be calculated using Equation 1. See Section 9.2.2.11 for additional information.

Equation 1.

where

• V_ON is the desired typical start-up input voltage for the circuit being designed

Note that since the EN/SYNC pin can also be used as an external synchronization clock input. A blanking time, t_B, is applied to the enable logic after a clock edge is detected. Any logic change within the blanking time is ignored. Blanking time is not applied when the device is in shutdown mode. The blanking time ranges from 4 µs to 28 µs. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs.