ZHCSL10C March 2020 – June 2021 LM61440-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 说明（续）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 EN/SYNC Uses for Enable and VIN UVLO
- 9.3.2 EN/SYNC Pin Uses for Synchronization
- 9.3.3 Clock Locking
- 9.3.4 Adjustable Switching Frequency
- 9.3.5 PGOOD Output Operation
- 9.3.6 Internal LDO, VCC UVLO, and BIAS Input
- 9.3.7 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
- 9.3.8 Adjustable SW Node Slew Rate
- 9.3.9 Spread Spectrum
- 9.3.10 Soft Start and Recovery From Dropout
- 9.3.11 Output Voltage Setting
- 9.3.12 Overcurrent and Short Circuit Protection
- 9.3.13 Thermal Shutdown
- 9.3.14 Input Supply Current
- 9.4 Device Functional Modes
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Application
- 10.2.1 Design Requirements
- 10.2.2
Detailed Design Procedure
- 10.2.2.1 Choosing the Switching Frequency
- 10.2.2.2 Setting the Output Voltage
- 10.2.2.3 Inductor Selection
- 10.2.2.4 Output Capacitor Selection
- 10.2.2.5 Input Capacitor Selection
- 10.2.2.6 BOOT Capacitor
- 10.2.2.7 BOOT Resistor
- 10.2.2.8 VCC
- 10.2.2.9 BIAS
- 10.2.2.10 CFF and RFF Selection
- 10.2.2.11 External UVLO
- 10.2.3 Application Curves
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
9.3.5 PGOOD Output Operation
The PGOOD function is implemented to replace a discrete reset device, reducing BOM count and cost. The PGOOD pin voltage goes low when the feedback voltage is outside of the specified PGOOD thresholds (see Figure 8-8). This can occur in current limit and thermal shutdown, as well as while disabled and during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions that are shorter than tPGDFLT_FALL do not trip the power-good flag. Power-good operation can be best understood by referring to Figure 9-6.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic supply or VOUT. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid as long as the input voltage is ≥ 1 V (typical).
Figure 9-6 PGOOD Timing Diagram (Excludes OV Events)| FAULT CONDITION INITIATED | FAULT CONDITION ENDS (AFTER WHICH tPGDFLT(rise) MUST PASS BEFORE PGOOD OUTPUT IS RELEASED)(1) |
|---|---|
| VOUT < VOUT-target × PGDUV AND t > tPGDFLT(fall) | Output voltage in regulation: VOUT-target × (PGDUV + PGDHYST) < VOUT < VOUT-target × (PGDOV - PGDHYST) (See Figure 8-8) |
| VOUT > VOUT-target × PGDOV AND t > tPGDFLT(fall) | Output voltage in regulation |
| TJ > TSD_R | TJ < TSD_F AND output voltage in regulation |
| EN < VEN Falling | EN > VEN Rising AND output voltage in regulation |
| VCC < VCC_UVLO - VCC_UVLO_HYST | VCC > VCC_UVLO AND output voltage in regulation |