The LM61440 reduces frequency whenever output voltage is high. This function is enabled whenever Comp, an internal signal, is low and there is an offset between the regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when the part is completely unloaded.

In auto mode, once output current drops below approximately 1/10th the rated current of the part, output resistance increases so that output voltage is 1% high while the buck is completely unloaded.

Figure 8-17 Steady State Output Voltage versus Output Current in Auto Mode

In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed on V_OUT. If the DC offset on V_OUT is not acceptable, a dummy load at V_OUT or FPWM Mode can be used to reduce or eliminate this offset.