Once a valid synchronization signal is detected, a clock locking procedure is initiated. The LM62440-Q1 receives this signal over the MODE/SYNC pin. After approximately 2048 pulses, the clock frequency completes a smooth transition to the frequency of the synchronization signal without output variation. Note that while the frequency is adjusted suddenly, phase is maintained so the clock cycle that lies between operation at the default frequency and at the synchronization frequency is of intermediate length. This eliminates very long or very short pulses. Once frequency is adjusted, phase is adjusted over a few tens of cycles so that rising synchronization edges correspond to rising SW node pulses. See Figure 9-12.

Pulses four and synchronization signal is detected. After the pulse, approximately 2048 ready to synchronize and frequency is adjusted using a glitch free technique. Later, phase is locked.

Figure 9-12 Synchronization Process

Also note that the LM62440-Q1 turns on spread spectrum after the first edge in the synchronization pulse. See the MODE/SYNC pin description in the Section 7. Upon adjustment of frequency on the approximate 2048th pulse, spread spectrum is turned off. Finally, if the part runs at reduced frequency due to low or high input voltage or during current limit, frequency lock does not occur until the condition causing low frequency operation has been removed.