Because V_OUT = 5 V in this design, the BIAS pin is tied to V_OUT to reduce LDO power loss. The output voltage is supplying the LDO current instead of the input voltage. The power saving is I_LDO × (V_IN – V_OUT). The power saving is more significant when V_IN >> V_OUT and with higher frequency operation. To prevent V_OUT noise and transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, can be added between V_OUT and BIAS. A bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise. Note the maximum allowed voltage on the BIAS pin is 16 V.