ZHCSL46D March   2020  – June 2021 LM62440-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 计时特性
    7. 8.7 Systems Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  EN Uses for Enable and VIN UVLO
      2. 9.3.2  MODE/SYNC Pin Operation
        1. 9.3.2.1 Level-Dependent MODE/SYNC Pin Control
        2. 9.3.2.2 Pulse-Dependent MODE/SYNC Pin Control
        3. 9.3.2.3 Clock Locking
      3. 9.3.3  PGOOD Output Operation
      4. 9.3.4  Internal LDO, VCC UVLO, and BIAS Input
      5. 9.3.5  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      6. 9.3.6  Adjustable SW Node Slew Rate
      7. 9.3.7  Spread Spectrum
      8. 9.3.8  Soft Start and Recovery From Dropout
      9. 9.3.9  Output Voltage Setting
      10. 9.3.10 Overcurrent and Short Circuit Protection
      11. 9.3.11 Thermal Shutdown
      12. 9.3.12 Input Supply Current
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 Auto Mode - Light Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode - Light Load Operation
        4. 9.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 9.4.3.5 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Choosing the Switching Frequency
        2. 10.2.2.2  Setting the Output Voltage
        3. 10.2.2.3  Inductor Selection
        4. 10.2.2.4  Output Capacitor Selection
        5. 10.2.2.5  Input Capacitor Selection
        6. 10.2.2.6  BOOT Capacitor
        7. 10.2.2.7  BOOT Resistor
        8. 10.2.2.8  VCC
        9. 10.2.2.9  BIAS
        10. 10.2.2.10 CFF and RFF Selection
        11. 10.2.2.11 External UVLO
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground and Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.3.4 Internal LDO, VCC UVLO, and BIAS Input

The VCC pin is the output of the internal LDO used to supply the control circuits of the LM62440-Q1. The nominal output is 3 V to 3.3 V. The BIAS pin is the input to the internal LDO. This input can be connected to VOUT to provide the lowest possible input supply current. If the BIAS voltage is less than 3.1 V, VIN1 and VIN2 directly powers the internal LDO.

To prevent unsafe operation, VCC has a UVLO that prevents switching if the internal voltage is too low. See VCC_UVLO and VCC_UVLO_HYST in Section 8.5. Note that these UVLO values and the dropout of the LDO are used to derive minimum VIN_OPERATE and VIN_OPERATE_H values.
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