ZHCSL46D March 2020 – June 2021 LM62440-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Description (continued)
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 EN Uses for Enable and VIN UVLO
- 9.3.2 MODE/SYNC Pin Operation
- 9.3.3 PGOOD Output Operation
- 9.3.4 Internal LDO, VCC UVLO, and BIAS Input
- 9.3.5 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
- 9.3.6 Adjustable SW Node Slew Rate
- 9.3.7 Spread Spectrum
- 9.3.8 Soft Start and Recovery From Dropout
- 9.3.9 Output Voltage Setting
- 9.3.10 Overcurrent and Short Circuit Protection
- 9.3.11 Thermal Shutdown
- 9.3.12 Input Supply Current
- 9.4 Device Functional Modes
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Application
- 10.2.1 Design Requirements
- 10.2.2
Detailed Design Procedure
- 10.2.2.1 Choosing the Switching Frequency
- 10.2.2.2 Setting the Output Voltage
- 10.2.2.3 Inductor Selection
- 10.2.2.4 Output Capacitor Selection
- 10.2.2.5 Input Capacitor Selection
- 10.2.2.6 BOOT Capacitor
- 10.2.2.7 BOOT Resistor
- 10.2.2.8 VCC
- 10.2.2.9 BIAS
- 10.2.2.10 CFF and RFF Selection
- 10.2.2.11 External UVLO
- 10.2.3 Application Curves
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
10.2.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the converter in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum of 10 μF of ceramic capacitance is required on the input of the device. This must be rated for at least the maximum input voltage that the application requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. In addition, a small case size 100-nF ceramic capacitor must be used at each input/ground pin pair, VIN1/PGND1 and VIN2/PGND2, immediately adjacent to the converter. This provides a high-frequency bypass for the control circuits internal to the device. These capacitors also suppress SW node ringing, which reduces the maximum voltage present on the SW node and EMI. The two 100 nF must also be rated at 50 V with an X7R or better dielectric. The VQFN-HR (RJR) package provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus improving the effectiveness of the input bypassing. In this example, two 4.7-μF and two 100-nF ceramic capacitors are used, one at each VIN/PGND location. A single 10-μF can also be used on one side of the package.
Many times, it is desirable and necessary to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially true if long leads or traces are used to connect the input supply to the converter. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitors. The approximate worst case RMS value of this current can be calculated from Equation 10 and must be checked against the manufacturers' maximum ratings.
