Once a valid synchronization signal is detected, a clock locking procedure is initiated. After approximately 2048 pulses, the clock frequency abruptly changes to the frequency of the synchronization signal. While the frequency adjusts suddenly, phase is maintained so the clock cycle lying between operation at the default and synchronization frequencies is of intermediate length. There are no very long or very short pulses. Once frequency is adjusted, phase is adjusted over a few tens of cycles so that rising synchronization edges correspond to rising the SW node pulses. See Figure 8-5.

At pulse 4, the synchronization signal is detected. After approximately pulse 2048, it is ready to synchronize and the frequency is adjusted using a glitch-free technique. Later, phase is locked.

Figure 8-5 Synchronization Process