A clock locking procedure initiates after a valid synchronization signal is detected. The LM634x0-Q1 receives this signal at the EN/SYNC pin. After approximately 2048 pulses, the clock frequency completes a smooth transition to the frequency of the synchronization signal without output voltage variation. Note that when the frequency is adjusted suddenly, the phase is maintained so the clock cycle that lies between operation at the default frequency and at the synchronization frequency is of intermediate length. This action eliminates very long or very short pulses. After the frequency is adjusted, the phase is adjusted over a few tens of cycles so that rising synchronization edges correspond to rising switch (SW) node pulses. See Figure 7-3.

The synchronization signal is detected after four pulses. The converter is ready to synchronize after approximately 2048 pulses, and the frequency is adjusted using a glitch-free technique. Phase locking is subsequently achieved.

Figure 7-3 Synchronization Process

Note also that the LM634x0-Q1 turns on spread spectrum after the first edge in the synchronization pulse. See the EN/SYNC pin description in Pin Configuration and Functions. Upon adjustment of the frequency at the approximate 2048^th pulse, spread spectrum is turned off. Finally, if the converter runs at reduced switching frequency due to low or high input voltage or during current limit, frequency lock does not occur until the condition causing low-frequency operation has been removed.