5 Pin Configuration and Functions

LM63440-Q1 LM63460-Q1 22-Pin Enhanced HotRod ™ QFNRYF Package(Top View)

Figure 5-1 22-Pin Enhanced HotRod ^™ QFNRYF Package(Top View)

Table 5-1 Pin Functions

PIN		TYPE^⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE^⁽¹⁾	DESCRIPTION
CBOOT	1	P	High-side driver supply rail. Connect a 100nF capacitor between SW and CBOOT. An internal bootstrap diode connects to VCC and allows the bootstrap capacitor to charge when SW is low.
NC	2	—	No internal connection
BIAS	3	P	Input to the internal LDO. Connect to the output voltage point to improve efficiency. Connect an optional high-quality 0.1µF to 1µF capacitor from this pin to GND for improved noise immunity. If the output voltage is above 12V, connect BIAS to GND.
VCC	4	O	Internal LDO output. VCC supplies the internal control circuits. Do not connect to any external loads. Connect a high-quality 1µF capacitor from VCC to GND.
FB	5	I	Output voltage feedback input to the internal control loop. Connect to the output voltage sense point for fixed 3.3V or 5V output voltage settings. Connect to a feedback divider tap point to set an adjustable output voltage. Do not float or connect to GND.
PGOOD	6	O	Open-drain power-good status indicator output. Pull up PGOOD to a suitable voltage supply through a current-limiting resistor. High = power OK, low = fault. The PGOOD output goes low when EN = low, V_IN > 1V.
RT	7	I/O	Connect a resistor from RT to GND with a value between 5.76kΩ and 66.5kΩ to set the switching frequency between 200kHz and 2.2MHz. Do not float or connect directly to GND.
EN/SYNC	8	I	Precision enable input. High = on, Low = off. EN/SYNC can be connected to VIN. Precision enable allows this pin to be used as an adjustable input voltage UVLO. See Precision Enable and Input Voltage UVLO (EN). Do not float. EN/SYNC also functions as a synchronization input pin, triggering on the rising edge of the external clock signal. Use a capacitor to AC couple the clock signal to EN/SYNC. When synchronized to an external clock, the converter operates in FPWM mode and disables the PFM light-load mode. See Section 7.3.5.
NC	9	—	No internal connection
VIN2	10	P	Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. A low-impedance connection must be provided to VIN1.
NC	11	—	No internal connection
PGND2	12	G	Power-ground connection to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2.
NC	13	—	No internal connection
SW1	14	P	Switch node of the converter. Connect to the output inductor.
SW2	15
SW3	16
NC	17	—	No internal connection
PGND1	18	G	Power ground to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1.
NC	19	—	No internal connection
VIN1	20	P	Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. A low-impedance connection must be provided to VIN2.
NC	21	—	No internal connection
SW4	22	P	Switch node of the converter. Connect to the bootstrap capacitor.
GND	–	G	Exposed pad of the package internally connected to ground. The exposed pad must be connected to the PCB inner-layer system ground plane or planes using numerous thermal vias to reduce thermal impedance. See Layout Guidelines.

(1) P = Power, G = Ground, I = Input, O = Output