ZHCSLU1B October   2022  – August 2024 LM64440-Q1 , LM64460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
    2. 5.2 Pinout Design for Clearance and FMEA
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Systems Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Output Voltage Setpoint (FB)
      3. 7.3.3  Precision Enable and Input Voltage UVLO (EN)
      4. 7.3.4  MODE/SYNC Operation
        1. 7.3.4.1 Level-Dependent MODE/SYNC Control
        2. 7.3.4.2 Pulse-Dependent MODE/SYNC Control
      5. 7.3.5  Clock Locking
      6. 7.3.6  Power-Good Monitor (PGOOD)
      7. 7.3.7  Bias Supply Regulator (VCC, BIAS)
      8. 7.3.8  Bootstrap Voltage and UVLO (CBOOT)
      9. 7.3.9  Spread Spectrum
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Overcurrent and Short-Circuit Protection
      12. 7.3.12 Thermal Shutdown
      13. 7.3.13 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode – Light-Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Foldback
        3. 7.4.3.3 FPWM Mode – Light-Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – Automotive Synchronous 6A Buck Regulator at 2.1MHz
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Design 2 – Automotive Synchronous 4A Buck Regulator at 2.1MHz
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.2.2.2  Setting the Output Voltage
          3. 8.2.2.2.3  Choosing the Switching Frequency
          4. 8.2.2.2.4  Inductor Selection
          5. 8.2.2.2.5  Output Capacitor Selection
          6. 8.2.2.2.6  Input Capacitor Selection
          7. 8.2.2.2.7  Bootstrap Capacitor
          8. 8.2.2.2.8  VCC Capacitor
          9. 8.2.2.2.9  BIAS Power Connection
          10. 8.2.2.2.10 Feedforward Network
          11. 8.2.2.2.11 Input Voltage UVLO
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

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机械数据 (封装 | 引脚)
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订购信息

8.2.1.1 Design Requirements

Table 8-1 shows the intended input, output, and performance parameters for this application example. The converter operates in dropout during cold crank when the input voltage decreases to 5V, with the output voltage slightly below the 5V setpoint.

Table 8-1 Design Parameters
DESIGN PARAMETER VALUE
Input voltage range (for constant fSW) 6V to 18V
Minimum transient input voltage, cold crank 5V
Maximum transient input voltage, load dump 36V
Output voltage and full-load current 5V, 6A
Switching frequency 2.1MHz
IC input current, no-load < 10µA
IC shutdown current < 1µA

Table 8-2 gives the selected buck converter power-stage components with availability from multiple vendors. This design uses a low-DCR inductor and all-ceramic output capacitor implementation.

Table 8-2 List of Materials for Application Circuit 1
REF DES QTY SPECIFICATION VENDOR (1) PART NUMBER
CIN 2 10µF, 50V, X7R, 1206, ceramic, AEC-Q200 Samsung CL31Y106KBKVPNE
TDK CGA5L1X7R1H106K
10µF, 50V, X7S, 1210, ceramic, AEC-Q200 Murata GCM32EC71H106KA03
TDK CGA6P3X7S1H106M
COUT 2 47µF, 6.3V, X7R, 1210, ceramic, AEC-Q200 Murata GCM32ER70J476KE19L
47µF, 10V, X7S, 1210, ceramic, AEC-Q200 TDK CGA6P1X7S1A476M
Murata GCM32EC71A476KE02
3 22µF, 16V, X7R, 1210, ceramic, AEC-Q200 TDK CGA6P1X7R1C226M
LO 1 0.76µH, 4.9mΩ, 11.8A, 4.0mm × 4.0mm × 3.1mm, AEC-Q200 Coilcraft XGL4030-761MEC
1µH, 9.1mΩ, 7.9A, 4.2mm × 4.0mm × 2.1mm, AEC-Q200 Cyntec VCHA042A-1R0M
1µH, 9.6mΩ, 14.7A, 5.3mm × 5.1mm × 3.0mm, AEC-Q200 TDK SPM5030VT-1R0M-D
1µH, 12mΩ, 11.6A, 4.1mm × 4.1mm × 3.1mm, AEC-Q200 Würth Electronik 74438357010
U1 1 LM64460-Q1 synchronous buck converter, AEC-Q100 Adjustable Texas Instruments LM64460APPQRYFRQ1
Fixed 5V LM64460CPPQRYFRQ1
(1) See the Third-Party Products Disclaimer.

More generally, the LM64460-Q1 converter is designed to operate with a wide range of external components and system parameters. However, the integrated loop compensation is optimized for a certain range of buck inductance and output capacitance. As a starting point, Table 8-3 provides typical component values for several common application configurations.

Table 8-3 Typical External Component Values
fSW (kHz) VOUT (V) LO (µH) COUT-EFF(min) (µF) Typical COUT Components
(1210, X7R)		 RFBT (kΩ) RFBB (kΩ) CFF (pF) RFF (kΩ)
2100 3.3 0.68 50 3 × 47µF, 6.3V or 4 × 22µF, 16V 100 43.2 10 1
2100 5 0.76 30 2 × 47µF, 10V or 3 × 22µF, 16V 100 24.9 10 1
400 1.8 2.2 120 3 × 100µF, 4V 80.6 100 22 1
400 3.3 3.3 70 3 × 47µF, 6.3V or 5 × 22µF, 16V 100 43.2 15 1
400 5 4.7 50 3 × 47µF, 10V or 4 × 22µF, 16V 100 24.9 15 1
400 12 6.8 20 3 × 22µF, 25V 100 9.09 4.7 1

Note that the minimum output capacitances listed in Table 8-3 represents effective values for ceramic capacitors derated for DC bias voltage and temperature.
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