In systems where there is a large amount of capacitance on the VDD node, the LM73-Q1 power supply ramp-up time can become excessively long. Slow power-supply ramp times may result in abnormal temperature readings. A linear power-on-ramp of less than 0.7 V/msec and an exponential ramp with an RC time constant of more than 1.25 msec is categorized as a slow power-supply ramp. To avoid errors, use the power up sequence described below.

The software reset sequence is as follows:

1. Allow V_DD to reach the specified minimum operating voltage, as specified in the Recommended Operating Conditions section.
2. Write a 1 to the Full Power Down bit, Bit 7 of the Configuration Register, and hold it high for the specified maximum conversion time for the initial default of 11-bits resolution. This ensures that a complete reset operation has occurred. See the Temperature Conversion Time specifications within the Temperature-to-Digital Converter Characteristics for more details.
3. Write a 0 to the Full Power Down bit to restore the LM73-Q1 to normal mode.