ZHCST56 September   2023 LM74700D-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8. 7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 功能方框图
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage
      2. 9.3.2 Charge Pump
      3. 9.3.3 Gate Driver
      4. 9.3.4 Enable
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Conduction Mode
        1. 9.4.2.1 Regulated Conduction Mode
        2. 9.4.2.2 Full Conduction Mode
        3. 9.4.2.3 Reverse Current Protection Mode
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Design Considerations
        2. 10.2.2.2 MOSFET Selection
        3. 10.2.2.3 Charge Pump VCAP, Input and Output Capacitance
      3. 10.2.3 Selection of TVS Diodes for 12-V Battery Protection Applications
      4. 10.2.4 Selection of TVS Diodes and MOSFET for 24-V Battery Protection Applications
      5. 10.2.5 Application Curves
      6. 10.2.6 OR-ing Application Configuration
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

6.6 Switching Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(ANODE) = 12 V, C(VCAP) = 0.1 µF, V(EN) = 3.3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENTDLY Enable (low to high) to Gate Turn On delay V(VCAP) > V(VCAP UVLOR) 75 110 µs
tReverse delay Reverse voltage detection to Gate Turn Off delay V(ANODE) – V(CATHODE) = 100 mV to –100 mV 0.45 0.75 µs
tReverse delay Reverse voltage detection to Gate Turn Off delay V(ANODE) – V(CATHODE) = 100 mV to –100 mV
V(ANODE) = 48 V		 0.45 µs
tForward recovery Forward voltage detection to Gate Turn On delay V(ANODE) – V(CATHODE) = –100 mV to 700 mV 1.4 2.6 µs
tForward recovery Forward voltage detection to Gate Turn On delay V(ANODE) – V(CATHODE) = –100 mV to 700 mV
V(ANODE) = 48 V		 1.4 µs
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