The LM76005-Q1 has an internal LDO generating VCC voltage for control circuitry and MOSFET drivers. The nominal voltage for VCC is 3.29 V. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close as possible to the pin and properly grounded. Do not load or short the VCC pin to ground during operation. Shorting the VCC pin to ground during operation can damage the device.

A UVLO prevents the LM76005-Q1 from operating until the VCC voltage exceeds V_{CC_UVLO}. The V_{CC_UVLO} threshold is 3.14 V and has approximately 565 mV of hysteresis, so the device operates until V_CC drops below 2.575 V (typical). Hysteresis prevents the device from turning off during power up if V_IN droops due to input current demands.

The LDO can generate V_CC from two inputs: the supply voltage V_IN and the BIAS input. The LDO power loss is calculated by I_LDO × (V_INLDO – V_OUTLDO). The higher the difference between the input and output voltages of the LDO, the more losses occur to supply the same LDO output current. The BIAS input is designed to reduce the difference of the input and output voltages of the LDO to improve efficiency, especially at light load. TI recommends tying the BIAS pin to V_OUT when the output voltage is equal to or greater than 3.3 V and less than 18 V. Tie the BIAS pin to ground for applications less than 3.3 V or greater than 18 V. BIAS can also tie to external voltage source if available to improve efficiency. When used, TI recommends a 1-µF to 10-µF high-quality ceramic capacitor be used to bypass the BIAS pin to ground. If there is high-frequency noise or voltage spikes present on V_OUT (during transient events or fault conditions), TI recommends connecting a resistor (1 to 10 Ω) between V_OUT and BIAS.

The V_CC voltage is typically 3.29 V. When the LM76005-Q1 is operating in PFM mode with frequency foldback, V_CC voltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve efficiency at very light loads.