The LM76005-Q1 has a built-in power-good flag shown on the PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage below 12 V). The pin can sink 5 mA of current and maintain its specified logic low level. A typical range of pullup resistor value is 10 kΩ to 100 kΩ. When the FB voltage is outside the power-good band, +10% above and –10% below the internal reference V_REF typically, the PGOOD switch is turned on, and the PGOOD pin voltage is pulled to ground. When the FB is 2.5% (typical) closer to FB than the PGOOD threshold, the PGOOD switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. Both rising and falling edges of the power-good flag have a built-in 140-µs (typical) deglitch delay. To pull up the PGOOD pin to a voltage higher than 15 V, a resistor divider can be used to divide the voltage down.

Figure 7-8 PGOOD Resistor Divider

For given pullup voltage, V_PU, the desired voltage on PGOOD pin, V_PG, and R_PGT chosen, use Equation 11 to calculate R_PGB:

Equation 11.