8.3.5.3 FAULT Response

The FLT open-drain output asserts (active low) under following conditions:

• Fault events such as undervoltage, overvoltage, overload, reverse current and thermal shutdown conditions
• When the device enters low current shutdown mode when SHDN is pulled low
• During start-up when the internal FET GATE is not fully enhanced (for example: V_OUT has not reached V_IN).

The FLT output does not assert in the event of reverse voltage on Input.

The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions without the need for an external circuitry.

The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the internal FET is fully enhanced and V_OUT has reached V_IN. The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy load is applied by the downstream converters. Rising deglitch delay is determined by t_PGOOD(degl) = Maximum {(900 + 20 × C_(dVdT)), t_PGOODR}, where C_(dVdT) is in nF and t_PGOOD(degl) is in µs. FLT can be left open or connected to RTN when not used. V_(IN) falling below V_(PORF) resets FLT.