10.1 Layout Guidelines

• Place the input capacitor as close as possible to the IC.
• Keep traces short between the IC and the C_D capacitor to ensure the timing delay is as accurate as possible.

10.2 Layout Example

Figure 18 and Figure 19 are layout examples for the LM8365, which is taken from the LM8365EVM. For information on the operation and schematic of the EVM, see the LM8365EVM User's Guide (SNVU493).

Figure 18. Layout Example

Figure 19. Top Layer Layout