7.3.6.3.1 Output Mode 1 - Dual Lane

In Dual Lane mode each input channel has its own data output presented at 16x the pixel clock rate. A frame signal (TXFRM) is output at the pixel clock rate with the rising edge occurring coincident with the transition of the MSB of the data. In Sample/Hold Modes of operation, the falling edge is coincident with the transition of bit 7 of the data. In CDS Mode, the falling edge of TXFRM toggles between the transition of bit 9 and bit 7 of the data. A differential clock is also output with transitions aligned with the center of the data eye. Data rates for Dual Lane mode range from 80 Mbps, with a 5-MHz clock, up to 640 Mbps, with a 40-MHz clock.

Figure 24. Dual Lane LVDS Output Timing Diagram