7.3.6.3.2 Output Mode 2 - Quad Lane

In Quad Lane mode each input channel is split into two data lanes which are presented at 8x the pixel rate. The MSBs (bits 13 through 7) will be presented to one channel while the LSBs (bits 6 through 0) will be presented to the other. A frame signal is run at the pixel clock rate with the rising edge coincident with the transition of the MSB of the data and the falling edge coincident with the transition of bits 10 and 3 of the data lanes for an odd output value, and coincident with the transition of bits 11 and 4 for a even output value. A differential clock is also output with rising edge transitions aligned within each data eye. Data rates for Quad Lane mode range from 40 Mbps, with a 5-MHz clock, up to 320 Mbps, with a 40-MHz clock.

Figure 25. Quad Lane LVDS Data Output Timing Diagram