10.1 Layout Guidelines

The layout of the LMG1020 is critical to its performance and functionality. The LMG1020 is available in a WCSP ball-grid array package, which enables low-inductance connection to a BGA-type GaN FET. Figure 15 shows the recommended layout of the LMG1020 with a ball-grid array GaN FET. Figure 16 presents a layout of LMG1020 with a 0.1 µF feed-through capacitor and a larger 1uF capacitor.

A four-layer or higher layer count board is required to reduce the parasitic inductances of the layout to achieve suitable performance. To minimize inductance and board space, resistors and capacitors in the 0201 package are used here. The gate drive power loss must be calculated to ensure an 0201 resistor will be able to handle the power level.