Due to the intrinsic nature of enhancement mode GaN FETs, the source-to-drain voltage of the bottom switch is usually higher than a diode forward voltage drop when the gate is pulled low. This causes negative voltage on HS pin. Moreover, this negative voltage transient may become even more pronounced due to the effects of board layout and device drain/source parasitic inductances. With high-side driver using the floating bootstrap configuration, negative HS voltage can lead to an excessive bootstrap voltage, which can damage the high-side GaN FET. The LMG1205 solves this problem with an internal clamping circuit that prevents the bootstrap voltage from exceeding 5 V typical. The clamping circuit works by opening an internal switch in series with the internal bootstrap diode when the bootstrap voltage exceeds the threshold, preventing further charging. The clamping circuit has a delay of about 270 ns between the threshold being exceeded and charging being stopped. In addition, the clamping circuit is bypassed if an external bootstrap diode is used.