To maximize the efficiency benefits of fast switching, it is extremely important to optimize the board layout such that the power loop impedance is minimal. When using a multilayer board (more than 2 layers), power loop parasitic impedance is minimized by having the return path to the input capacitor (between VIN and PGND), small and directly underneath the first layer as shown in Figure 8-7 and Figure 8-8. Loop inductance is reduced due to flux cancellation as the return current is directly underneath and flowing in the opposite direction.

Insufficient attention to the above power loop layout guidelines can result in excessive overshoot and undershoot on the switch node.

It is also critical that the VCC capacitors and the bootstrap capacitors are as close as possible to the device and in the first layer. Carefully consider the AGND connection of LMG2100R026 device. It must NOT be directly connected to PGND so that PGND noise does not directly shift AGND and cause spurious switching events due to noise injected in HI and LI signals.

Refer LMG2100 EVM for an actual layout based on these recommendations.