ZHCSNW8A
October 2022 – December 2022
LMG2610
PRODUCTION DATA
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
7.1
GaN Power FET Switching Parameters
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
GaN Power FET Switching Capability
8.3.2
Turn-On Slew-Rate Control
8.3.3
Current-Sense Emulation
8.3.4
Bootstrap Diode Function
8.3.5
Input Control Pins (EN, INL, INH)
8.3.6
INL - INH Interlock
8.3.7
AUX Supply Pin
8.3.7.1
AUX Power-On Reset
8.3.7.2
AUX Under-Voltage Lockout (UVLO)
8.3.8
BST Supply Pin
8.3.8.1
BST Power-On Reset
8.3.8.2
BST Under-Voltage Lockout (UVLO)
8.3.9
Over-Current Protection
8.3.10
Over-Temperature Protection
8.3.11
Fault Reporting
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Turn-On Slew-Rate Design
9.2.2.2
Current-Sense Design
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Solder-Joint Stress Relief
9.4.1.2
Signal-Ground Connection
9.4.1.3
CS Pin Signal
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
接收文档更新通知
10.3
支持资源
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
术语表
11
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
RRG|40
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsnw8a_oa
zhcsnw8a_pm
9.4.2
Layout Example
Figure 9-2
PCB Top Layer (First Layer)
Figure 9-3
PCB Inner Layer (Second Layer)
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