ZHCSM56D September 2020 – March 2022 LMG3422R030 , LMG3425R030
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 GaN FET Operation Definitions
- 9.3.2 Direct-Drive GaN Architecture
- 9.3.3 Drain-Source Voltage Capability
- 9.3.4 Internal Buck-Boost DC-DC Converter
- 9.3.5 VDD Bias Supply
- 9.3.6 Auxiliary LDO
- 9.3.7 Fault Detection
- 9.3.8 Drive Strength Adjustment
- 9.3.9 Temperature-Sensing Output
- 9.3.10 Ideal-Diode Mode Operation
- 9.4 Device Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
10.2 Typical Application
CAUTION: For applications where the drain slew rate is programmed for
greater than a typical 100 V/ns (RRDRV < 10 kΩ or VRDRV = 5 V), the
following application design modifications must be implemented to minimize the risk of LDO5V
pin damage.
- Remove C2.
- Put a 10-Ω resistor between the U1 LDO5V pin and C10. No other components must be between the resistor and the U1 LDO5V pin.
- Remove C12.
- Put a 10-Ω resistor between the U2 LDO5V pin and C27. No other components must be between the resistor and the U2 LDO5V pin.
Figure 10-1 Typical Half-Bridge
Application