ZHCSNN4B October 2020 – May 2022 LMG3422R050 , LMG3425R050
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 GaN FET Operation Definitions
- 9.3.2 Direct-Drive GaN Architecture
- 9.3.3 Drain-Source Voltage Capability
- 9.3.4 Internal Buck-Boost DC-DC Converter
- 9.3.5 VDD Bias Supply
- 9.3.6 Auxiliary LDO
- 9.3.7 Fault Detection
- 9.3.8 Drive Strength Adjustment
- 9.3.9 Temperature-Sensing Output
- 9.3.10 Ideal-Diode Mode Operation
- 9.4 Start Up Sequence
- 9.5 Safe Operation Area (SOA)
- 9.6 Device Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
12.2 Layout Examples
Correct layout of the LMG342xR050 and its surrounding components is essential for correct operation. The layouts shown here reflect the GaN device schematic in Figure 10-1. These layouts are shown to produce good results and is intended as a guideline. However, it can be possible to obtain acceptable performance with alternate layout schemes. Additionally, please refer to the land pattern example in Mechanical, Packaging, and Orderable Information for the latest recommended PCB footprint of the device.
The the top-layer layout and mid-layer layout are shown. The layouts are zoomed in to the LMG342xR050 U1 and U2 component placements. The mid-layer layout includes the outlines of the top level components to assist the reader in lining up the top-layer and mid-layer layouts.
Figure 12-1 Half-Bridge
Top-Layer Layout
Figure 12-2 Half-Bridge
Mid-Layer Layout