ZHCSNN4B October   2020  – May 2022 LMG3422R050 , LMG3425R050

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Times
      2. 8.1.2 Turn-Off Times
      3. 8.1.3 Drain-Source Turn-On Slew Rate
      4. 8.1.4 Turn-On and Turn-Off Switching Energy
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  GaN FET Operation Definitions
      2. 9.3.2  Direct-Drive GaN Architecture
      3. 9.3.3  Drain-Source Voltage Capability
      4. 9.3.4  Internal Buck-Boost DC-DC Converter
      5. 9.3.5  VDD Bias Supply
      6. 9.3.6  Auxiliary LDO
      7. 9.3.7  Fault Detection
        1. 9.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.7.2 Overtemperature Shutdown
        3. 9.3.7.3 UVLO Protection
        4. 9.3.7.4 Fault Reporting
      8. 9.3.8  Drive Strength Adjustment
      9. 9.3.9  Temperature-Sensing Output
      10. 9.3.10 Ideal-Diode Mode Operation
    4. 9.4 Start Up Sequence
    5. 9.5 Safe Operation Area (SOA)
      1. 9.5.1 Safe Operation Area (SOA) - Repetitive SOA
    6. 9.6 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Solder-Joint Reliability
      2. 12.1.2 Power-Loop Inductance
      3. 12.1.3 Signal-Ground Connection
      4. 12.1.4 Bypass Capacitors
      5. 12.1.5 Switch-Node Capacitance
      6. 12.1.6 Signal Integrity
      7. 12.1.7 High-Voltage Spacing
      8. 12.1.8 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 术语表
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
  • RQZ|54
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.1 Absolute Maximum Ratings

Unless otherwise noted: voltages are respect to GND(1)
MIN MAX UNIT
VDS Drain-source voltage, FET off 600 V
VDS(surge) Drain-source voltage, FET switching, surge condition(2) 720 V
VDS(tr)(surge) Drain-source transient ringing peak voltage, FET off, surge condition(2)(3) 800 V
Pin voltage VDD –0.3 20 V
LDO5V –0.3 5.5 V
VNEG –16 0.3 V
BBSW VVNEG–1 VVDD+0.5 V
IN –0.3 20 V
FAULT, OC, TEMP –0.3 VLDO5V+0.3 V
RDRV –0.3 5.5 V
ID(RMS) Drain RMS current, FET on 44 A
ID(pulse) Drain pulsed current, FET on, tp < 10 µs(4) –96 Internally Limited A
IS(pulse) Source pulsed current, FET off, tp < 1 µs 60 A
TJ Operating junction temperature(5) –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See Section 9.3.3 for an explanation of the switching cycle drain-source voltage ratings.
(3) t1 < 200 ns in Figure 9-1.
(4) The positive pulsed current must remain below the overcurrent threshold to avoid the FET being automatically shut off. The FET drain intrinsic positive pulsed current rating for tp < 10 µs is 96 A.
(5) Refer to the Electrical and Switching Characteristics Tables for junction temperature test conditions.
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