There are two types of current faults which can be detected by the driver: overcurrent fault and short-circuit fault.

The overcurrent protection (OCP) circuit monitors drain current and compares that current signal with an internally set limit I_T(OC). Upon detection of the overcurrent, the LMG3425R050 conducts cycle-by-cycle overcurrent protection as shown in Figure 7-4. In this mode, the GaN device is shut off when the drain current crosses the I_T(OC) plus a delay t_off(OC), but the overcurrent signal clears after the IN pin signal goes low. In the next cycle, the GaN device can turn on as normal. The cycle-by-cycle function can be used in cases where steady-state operation current is below the OCP level but transient response can still reach current limit, while the circuit operation cannot be paused. The cycle-by-cycle function also prevents the GaN device from overheating by overcurrent induced conduction losses.

The short-circuit protection (SCP) monitors the drain current and triggers if the di/dt of the current exceeds a threshold di/dt_T(SC) as the current crosses between the OC and SC thresholds. It performs this di/dt detection by delaying the OC detection signal by an amount t_OC,window and using a higher current SC detection threshold. If the delayed OC occurs before the non-delayed SC, the di/dt is below the threshold and an OC is triggered. If the SC is detected first, the di/dt is fast enough and the SC is detected as shown in Figure 7-5. This extremely high di/dt current would typically be caused by a short of the output of the half-bridge and can be damaging for the GaN to continue to operate in that condition. Therefore, if a short-circuit fault is detected, the GaN device is turned off with an intentionally slowed driver so that a lower overshoot voltage and ringing can be achieved during the turn-off event. This fast response circuit helps protect the GaN device even under a hard short-circuit condition. In this protection, the GaN device is shut off and held off until the fault is reset by either holding the IN pin low for a period of time defined in the Specifications or removing power from VDD.

During OCP or SCP in a half bridge, after the current reaches the upper limit and the device is turned off by protection, the PWM input of the device could still be high and the PWM input of the complementary device could still be low. In this case, the load current can flow through the third quadrant of the complementary device with no synchronous rectification. The high negative V_DS of the GaN device (–3 V to –5 V) from drain to source could lead to high third-quadrant loss, similar to dead-time loss but for a longer time.

For safety considerations, OCP allows cycle-by-cycle operation while SCP latches the device until reset. See the Fault Reporting section for information on how the OCP and SCP faults are reported.

Figure 7-4 Cycle-by-Cycle OCP Operation

Figure 7-5 Overcurrent Detection vs Short-Circuit Detection