Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware that the headline drain-source voltage cannot be used as an equivalent point to compare devices across technologies. The headline drain-source voltage of a silicon FET is set by the avalanche breakdown voltage. The headline drain-source voltage of a GaN FET is set by the long term reliability with respect to data sheet specifications.

Exceeding the headline drain-source voltage of a silicon FET can lead to immediate and permanent damage. Meanwhile, the breakdown voltage of a GaN FET is much higher than the headline drain-source voltage. For example, the breakdown voltage of the LMG3425R050 is more than 800V.

A silicon FET is usually the weakest link in a power application during an input voltage surge. Surge protection circuits must be carefully designed to ensure the silicon FET avalanche capability is not exceeded because it is not feasible to clamp the surge below the silicon FET breakdown voltage. Meanwhile, it is easy to clamp the surge voltage below a GaN FET breakdown voltage. In fact, a GaN FET can continue switching during the surge event which means output power is safe from interruption.

The LMG3425R050 drain-source capability is explained with the assistance of Figure 7-1. The figure shows the drain-source voltage versus time for a GaN FET for a single switch cycle in a switching application. No claim is made about the switching frequency or duty cycle. This device is not recommended for continuous voltage stress in non-switching applications.

Figure 7-1 Drain-Source Voltage Switching Cycle

The waveform starts before t₀ with the FET in the on state. At t₀ the GaN FET turns off and parasitic elements cause the drain-source voltage to ring at a high frequency. The peak ring voltage is designated V_DS(tr). The high frequency ringing has damped out by t₁. Between t₁ and t₂ the FET drain-source voltage is set by the characteristic response of the switching application. The characteristic is shown as a flat line, but other responses are possible. The voltage between t₁ and t₂ is designated V_DS(off). At t₂ the GaN FET is turned on at a non-zero drain-source voltage. The drain-source voltage at t₂ is designated V_{DS(switching)}. Unique V_DS(tr), V_DS(off) and V_{DS(switching)} parameters are shown because each can contribute to stress over the lifetime of the GaN FET.

The LMG3425R050 drain-source surge voltage capability is seen with the absolute maximum ratings V_{DS(tr)(surge)} and V_DS(surge) in the Specifications where V_{DS(tr)(surge)} maps to V_DS(tr) in Figure 7-1 and V_DS(surge) maps to both V_DS(off) and V_{DS(switching)} in Figure 7-1. More information about the surge capability of TI GaN FETs is found in A New Approach to Validate GaN FET Reliability to Power-line Surges Under Use-conditions.