ZHCSNE5D October 2020 – February 2024 LMG3522R030-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 GaN FET Operation Definitions
- 7.3.2 Direct-Drive GaN Architecture
- 7.3.3 Drain-Source Voltage Capability
- 7.3.4 Internal Buck-Boost DC-DC Converter
- 7.3.5 VDD Bias Supply
- 7.3.6 Auxiliary LDO
- 7.3.7 Fault Detection
- 7.3.8 Drive-Strength Adjustment
- 7.3.9 Temperature-Sensing Output
- 7.3.10 Ideal-Diode Mode Operation
- 7.4 Start-Up Sequence
- 7.5 Safe Operation Area (SOA)
- 7.6 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
- RQS|52
散热焊盘机械数据 (封装 | 引脚)
- RQS|52
订购信息
8.5.2 Layout Examples
Correct layout of the LMG3522R030-Q1 and its surrounding components is essential for correct operation. The layouts shown here reflect the GaN device schematic in Figure 8-1. These layouts are shown to produce good results and is intended as a guideline. However, it can be possible to obtain acceptable performance with alternate layout schemes. Additionally, please refer to the land pattern example in Mechanical, Packaging, and Orderable Information for the latest recommended PCB footprint of the device.
The the top-layer layout, mid-layer and bottom-layer layout are shown. The mid-layer layout includes the outlines of the top level components to assist the reader in lining up the top-layer and mid-layer layouts.
Figure 8-10 Half-Bridge
Top-Layer Layout
Figure 8-11 Half-Bridge
Third-Layer (Light Grey) and Bottom-Layer (Dark Grey)
Layout