The power loop, comprising of the two devices in the half bridge and the high-voltage bus capacitance, undergoes high di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic interference (EMI) can be reduced, as well as reducing voltage stress on the devices.

Place the power devices as close as possible to minimize the power loop inductance. The decoupling capacitors are positioned in line with the two devices. They can be placed close to either device. In Layout Examples, the devices are placed on the bottom layer and the decoupling capacitors are placed on the top layer. The PGND is placed on the top layer, the HVBUS is located on top and third layer, and the switching node is on the top layer. They are connected to the power devices on bottom layer with vias. Area of traces close to the devices are minimized by bottom layer in order to keep clearance between heatsink and conductors.

The power loop inductance can be estimated based on the ringing frequency f_ring of the drain-source voltage switching waveform based on the following equation

where C_ring is equal to C_OSS at the bus voltage (refer to Figure 6-8 for the typical value) plus the drain-source parasitic capacitance from the board and load inductor or transformer.

As the parasitic capacitance of load components is hard to character, it's recommended to capture the V_DS switching waveform without load components to estimate the power loop inductance. Typically, the power loop inductance of the Layout Example is around 2.5 nH.