ZHCSRV6A march 2023 – april 2023 LMG3526R030
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 GaN FET Operation Definitions
- 8.3.2 Direct-Drive GaN Architecture
- 8.3.3 Drain-Source Voltage Capability
- 8.3.4 Internal Buck-Boost DC-DC Converter
- 8.3.5 VDD Bias Supply
- 8.3.6 Auxiliary LDO
- 8.3.7 Fault Detection
- 8.3.8 Drive-Strength Adjustment
- 8.3.9 Temperature-Sensing Output
- 8.3.10 Ideal-Diode Mode Operation
- 8.3.11 Zero-Voltage Detection (ZVD)
- 8.4 Start-Up Sequence
- 8.5 Safe Operation Area (SOA)
- 8.6 Device Functional Modes
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
9.5.2 Layout Examples
Correct layout of the LMG3526R030 and its surrounding components is essential for correct operation. The layouts shown here reflect the GaN device schematic in Figure 9-1. These layouts are shown to produce good results and is intended as a guideline. However, it can be possible to obtain acceptable performance with alternate layout schemes. Additionally, please refer to the land pattern example in Mechanical, Packaging, and Orderable Information for the latest recommended PCB footprint of the device.
The the top-layer layout, mid-layer and bottom-layer layout are shown. The mid-layer layout includes the outlines of the top level components to assist the reader in lining up the top-layer and mid-layer layouts.
Figure 9-10 Half-Bridge
Top-Layer Layout
Figure 9-11 Half-Bridge
Third-Layer (Light Grey) and Bottom-Layer (Dark Grey)
Layout