ZVD Timing Specifications defines the switching timings related to the zero-voltage detection block, and the device’s drain-to-source voltage, IN pin signal, and ZVD output signals are demonstrated. When the device achieves ZVS, the ZVD pin outputs a pulse-signal with width T_{WD_ZVD}, and the delay time in between IN pin’s rising edge and ZVD pulse’s rising edge is defined as T_{DL_ZVD}. A certain third quadrant conduction time is required to allow the device detecting a zero-voltage switching, and T_{3rd_ZVD} indicates this timing.

Figure 7-3 ZVD Timing Specifications