SNLS285H April 2008 – May 2016 LMH0303
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | –0.5 | 3.6 | V | |
Input voltage (all inputs) | –0.3 | VCC + 0.3 | V | |
Output current | 28 | mA | ||
Lead temperature (soldering, 4 s) | 260 | °C | ||
Junction temperature | 125 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±8000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±2000 | |||
Machine model (MM) | ±400 |
MIN | NOM | MAX | UNIT | |
---|---|---|---|---|
Supply voltage (VCC – VEE) | 3.13 | 3.3 | 3.46 | V |
Operating junction temperature | 100 | °C | ||
Operating free air temperature, TA | –40 | 25 | 85 | °C |
THERMAL METRIC(1) | LMH0303 | UNIT | |
---|---|---|---|
RUM (WQFN) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 40.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 39.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 18.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 18.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VCMIN | Input common mode voltage | SDI, SDI | 1.6 + VSDI/2 | VCC – VSDI/2 | V | |
VSDI | Input voltage swing | Differential (SDI, SDI) | 100 | 2200 | mVP−P | |
VCMOUT | Output common mode voltage | SDO, SDO | VCC – VSDO | V | ||
VSDO | Output voltage swing (SDO, SDO) | Single-ended, 75-Ω load, RREF = 750 Ω 1% |
720 | 800 | 880 | mVP-P |
VIH | Input voltage high level | SD/HD, ENABLE | 2 | V | ||
VIL | Input voltage low level | SD/HD, ENABLE | 0.8 | V | ||
ICC | Supply current | SD/HD = 0, SDO/SDO enabled |
47 | 57 | mA | |
SD/HD = 1, SDO/SDO enabled |
40 | 47 | ||||
SDO/SDO disabled | 1.3 | 2.5 | ||||
SMBUS DC SPECIFICATIONS | ||||||
VSIL | Data, clock input low voltage | 0.8 | V | |||
VSIH | Data, clock input high voltage | 2.1 | VSDD | V | ||
ISPULLUP | Current through pullup resistor or current source |
VOL = 0.4 V | 4 | mA | ||
VSDD | Nominal bus voltage | 3 | 3.6 | V | ||
ISLEAKB | Input leakage per bus segment(3) | –200 | 200 | µA | ||
ISLEAKP | Input leakage per pin | –10 | 10 | µA | ||
CSI | Capacitance for SDA and SCL(3)(4) | 10 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DRSDI | Input data rate | 2970 | Mbps | |||
Tjit | Additive output jitter | 2.97 Gbps | 20 | psP-P | ||
1.485 Gbps | 18 | |||||
270 Mbps | 15 | |||||
tr,tf | Output rise time and fall time | SD/HD = 0, 20% to 80% | 90 | 130 | ps | |
SD/HD = 1, 20% to 80% | 400 | 800 | ||||
TMATCH | Mismatch in rise or fall time | SD/HD = 0 | 30 | ps | ||
SD/HD = 1 | 50 | |||||
TDCD | Duty cycle distortion | SD/HD = 0, 2.97 Gbps(2) | 27 | ps | ||
SD/HD = 0, 1.485 Gbps(2) | 30 | |||||
SD/HD = 1(2) | 100 | |||||
TOS | Output overshoot | SD/HD = 0(2) | 10% | |||
SD/HD = 1(2) | 8% | |||||
RLSDO | Output return loss | 5 MHz to 1.5 GHz(3) | 15 | dB | ||
1.5 GHz to 3 GHz(3) | 10 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSMB | Bus operating frequency | 10 | 100 | kHz | |
tBUF | Bus free time between stop and start condition | 4.7 | µs | ||
tHD:STA | Hold time after (repeated) start condition. After this period, the first clock is generated; at ISPULLUP = MAX |
4 | µs | ||
tSU:STA | Repeated start condition setup time | 4.7 | µs | ||
tSU:STO | Stop condition setup time | 4 | µs | ||
tHD:DAT | Data hold time | 300 | ns | ||
tSU:DAT | Data setup time | 250 | ns | ||
tLOW | Clock low period | 4.7 | µs | ||
tHIGH | Clock high period | 4 | 50 | µs | |
tF | Clock or data fall time | 300 | ns | ||
tR | Clock or data rise time | 1000 | ns | ||
tPOR | Time in which device must be operational after power on | 500 | ms |