SNLS323N August   2010  – January 2017 LMH0395

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Switching Characteristics for SPI Interface
    8. 6.8 Timing Requirements for SPI Interface
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Mute Reference (MuteREF)
      2. 7.3.2 Carrier Detect (CD) and Mute
      3. 7.3.3 Input Interfacing
      4. 7.3.4 Output Interfacing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto Sleep
    5. 7.5 Programming
      1. 7.5.1 SPI Register Access
        1. 7.5.1.1  SPI Transaction Overview
        2. 7.5.1.2  SPI Write
        3. 7.5.1.3  SPI Read
        4. 7.5.1.4  SPI Daisy-Chain Operation
        5. 7.5.1.5  SPI Daisy-Chain Write
        6. 7.5.1.6  SPI Daisy-Chain Read
        7. 7.5.1.7  SPI Daisy-Chain Read and Write Example
        8. 7.5.1.8  SPI Daisy-Chain Length Detection
        9. 7.5.1.9  Output Driver Adjustments and De-Emphasis Setting
        10. 7.5.1.10 Launch Amplitude Optimization
        11. 7.5.1.11 Cable Length Indicator (CLI)
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Interfacing to 3.3-V SPI
      2. 8.1.2 Crosstalk Immunity
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Dos and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

RUM Package
24-Pin WQFN (Non-SPI)
Top View
LMH0395 30115703.gif

Pin Functions – Pin Mode (Non-SPI) / SPI_EN = GND(1)

PIN TYPE DESCRIPTION
NO. NAME
1 VEE Ground Negative power supply (ground)
2 VEE Ground Negative power supply (ground)
3 SDI I, Analog Serial data true input
4 SDI I, Analog Serial data complement input
5 VEE Ground Negative power supply (ground)
6 SPI_EN I, LVCMOS SPI register access enable
This pin has an internal pulldown.
H = SPI register access mode
L = Pin mode
7 SDO1_DISABLE I, LVCMOS Output driver 1 (SDO1, SDO1) disable
This pin has an internal pullup.
H (or no connection) = Output driver 1 is in a high-impedance state
L = Output driver 1 is enabled
8 AEC+ I/O, Analog AEC loop filter external capacitor (1-µF) positive connection (capacitor is optional)
9 AEC- I/O, Analog AEC loop filter external capacitor (1-µF) negative connection (capacitor is optional)
10 BYPASS I, LVCMOS Equalization bypass
This pin has an internal pulldown.
H = Equalization is bypassed (no equalization occurs).
L = Normal operation
11 MUTEREF I, Analog Mute reference input that sets the threshold for CD and determines the maximum cable to be equalized before muting. MUTEREF may be either unconnected or connected to ground for normal CD operation. There is no MUTE in SPI Mode.
12 VEE Ground Negative power supply (ground)
13 VEE Ground Negative power supply (ground)
14 SDO0 O, LVDS Serial data output 0 complement
15 SDO0 O, LVDS Serial data output 0 true
16 VEE Ground Negative power supply (ground)
17 SDO1 O, LVDS Serial data output 1 complement
18 SDO1 O, LVDS Serial data output 1 true
19 AUTO SLEEP I, LVCMOS Auto Sleep
AUTO SLEEP has precedence over MUTE and BYPASS. This pin has an internal pullup.
H = When no input signal is detected, the device will power down and the outputs will be in a high impedance state.
L = Device will not enter auto power down.
20 VCC Power Positive power supply (+2.5 V)
21 MUTE I, LVCMOS Output mute
CD may be tied to this pin to inhibit the output when no input signal is present. MUTE has precedence over BYPASS. This pin has an internal pulldown.
H = Outputs are forced to a constant logic high state.
L = Outputs are enabled.
22 CD O, LVCMOS Carrier detect
H = No input signal detected.
L = Input signal detected.
23 VEE Ground Negative power supply (ground)
24 VCC Power Positive power supply (+2.5 V)
DAP VEE Ground Connect exposed DAP to negative power supply (ground). See Figure 22 for layout example
(1) The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.
RTW Package
24-Pin WQFN SPI Mode
Top View
LMH0395 30115707.gif

Pin Functions – SPI Mode / SPI_EN = VCC(1)

PIN I/O, TYPE DESCRIPTION
NO. NAME
1 VEE Ground Negative power supply (ground)
2 VEE Ground Negative power supply (ground)
3 SDI I, Analog Serial data true input
4 SDI I, Analog Serial data complement input
5 VEE Ground Negative power supply (ground)
6 SPI_EN I, LVCMOS SPI register access enable
This pin has an internal pulldown.
H = SPI register access mode
L = Pin mode
7 SDO1_DISABLE I, LVCMOS Output driver 1 (SDO1, SDO1) disable
This pin has an internal pullup
H (or no connection) = Output driver 1 is in a high-impedance state.
L = Output driver 1 is enabled.
8 AEC+ I/O, Analog AEC loop filter external capacitor (1-µF) positive connection (capacitor is optional)
9 AEC- I/O, Analog AEC loop filter external capacitor (1-µF) negative connection (capacitor is optional)
10 CD O, LVCMOS Carrier detect
H = No input signal detected.
L = Input signal detected.
11 MUTEREF I, Analog Mute reference input that sets the threshold for CD and determines the maximum cable to be equalized before muting. MUTEREF may be either unconnected or connected to ground for normal CD operation. There is no MUTE in SPI Mode
12 VEE Ground Negative power supply (ground)
13 SS (SPI) I, LVCMOS SPI slave select
This pin has an internal pullup.
14 SDO0 O, LVDS Serial data output 0 complement
15 SDO0 O, LVDS Serial data output 0 true
16 VEE Ground Negative power supply (ground)
17 SDO1 O, LVDS Serial data output 1 complement
18 SDO1 O, LVDS Serial data output 1 true
19 MISO (SPI) O, LVCMOS SPI Master Input / Slave Output
LMH0395 control data transmit
20 VCC Power Positive power supply (+2.5 V)
21 SCK (SPI) I, LVCMOS SPI serial clock input
22 MOSI (SPI) I, LVCMOS SPI Master Output / Slave Input
LMH0395 control data receive
This pin has an internal pulldown.
23 VEE Ground Negative power supply (ground)
24 VCC Power Positive power supply (+2.5 V)
DAP VEE Ground Connect exposed DAP to negative power supply (ground). See Figure 22 for layout example.
(1) The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.
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