ZHCSKE0B March   2017  – October 2019 LMH1208

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Pins and Thresholds
      2. 7.3.2 OUT0_SEL and SDI_OUT2_SEL Control
      3. 7.3.3 Input Signal Detect
      4. 7.3.4 Continuous Time Linear Equalizer (CTLE)
      5. 7.3.5 Output Driver Control
        1. 7.3.5.1 Line-Side Output Cable Driver (SDI_OUT1+, SDI_OUT2+)
          1. 7.3.5.1.1 Output Amplitude (VOD)
          2. 7.3.5.1.2 Output Pre-Emphasis
          3. 7.3.5.1.3 Output Slew Rate
          4. 7.3.5.1.4 Output Polarity Inversion
        2. 7.3.5.2 Host-Side 100-Ω Output Driver (OUT0±)
      6. 7.3.6 Status Indicators and Interrupts
        1. 7.3.6.1 SD_N (Signal Detect)
        2. 7.3.6.2 INT_N (Interrupt)
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transaction
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
        2. 7.4.2.2 SPI Write Transaction Format
        3. 7.4.2.3 SPI Read Transaction Format
        4. 7.4.2.4 SPI Daisy Chain
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SMPTE Requirements and Specifications
      2. 8.1.2 LMH1208 and LMH1228 Compatibility
    2. 8.2 Typical Applications
      1. 8.2.1 Dual Cable Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Distribution Amplifier
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Stack-Up and Ground References
      2. 10.1.2 High-Speed PCB Trace Routing and Coupling
      3. 10.1.3 Anti-Pads
      4. 10.1.4 BNC Connector Layout and Routing
      5. 10.1.5 Power Supply and Ground Connections
      6. 10.1.6 Footprint Recommendations
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 出口管制提示
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PD Power dissipation
Measured with PRBS10,
Operating at 11.88 Gbps,
VOD = default 		SDI_OUT1± enabled
SDI_OUT2± disabled
OUT0± disabled		 200 mW
SDI_OUT1± enabled
SDI_OUT2± disabled
OUT0± enabled		 250 mW
SDI_OUT1± enabled
SDI_OUT2± enabled
OUT0± disabled		 340 mW
SDI_OUT1± enabled
SDI_OUT2± enabled
OUT0± enabled		 385 mW
PDZ Power dissipation,
Power Save Mode		 Power Save Mode,
ENABLE = H, no signal applied at IN0±		 25 mW
IDD Current consumption,
Measured with PRBS10,
Operating at 11.88 Gbps,
VOD = default 		SDI_OUT1± enabled
SDI_OUT2± disabled
OUT0± disabled		 80 104 mA
SDI_OUT1± enabled
SDI_OUT2± disabled
OUT0± enabled		 100 125 mA
SDI_OUT1± enabled
SDI_OUT2± enabled
OUT0± disabled		 136 170 mA
SDI_OUT1± enabled
SDI_OUT2± enabled
OUT0± enabled		 154 190 mA
IDDZ Current consumption,
Power Save Mode		 Power Save Mode,
ENABLE = H, no signal applied at IN0±		 10 mA
IDDZ_PD Current consumption,
Power-Down Mode		 Power-Down Mode,
ENABLE = L, no signal applied at IN0±		 10 30 mA
LVCMOS DC SPECIFICATIONS
VIH Logic high input voltage 2-level input (SS_N, SCK, MOSI, SDI_OUT2_SEL, OUT0_SEL, ENABLE) 0.72 × VIN VIN + 0.3 V
2-level input (SCL, SDA) 0.7 × VIN 3.6 V
VIL Logic low input voltage 2-level input (SS_N, SCK, MOSI, SDI_OUT2_SEL, OUT0_SEL, ENABLE, SCL, SDA) 0 0.3 × VIN V
VOH Logic high output voltage IOH = –2 mA, (MISO) 0.8 × VIN VIN V
VOL Logic low output voltage IOL = 2 mA, (MISO) 0 0.2 × VIN V
IOL = 3 mA, (SD_N, SDA) 0.4 V
IIH Input high leakage current
(Vinput = VIN)		 LVCMOS (SDI_OUT2_SEL, ENABLE) 15 µA
LVCMOS (OUT0_SEL) 65 µA
LVCMOS (SD_N) 10 µA
SPI mode: LVCMOS (SS_N, SCK, MOSI) 15 µA
SMBus mode: LVCMOS (SCL, SDA) 10 µA
IIL Input low leakage current
(Vinput = GND)		 LVCMOS (SDI_OUT2_SEL, ENABLE) –50 µA
LVCMOS (OUT0_SEL) –15 µA
LVCMOS (SD_N) –10 µA
SPI mode: LVCMOS (SCK, MOSI) –15 µA
SPI mode: LVCMOS (SS_N) –50 µA
SMBus mode: LVCMOS (SCL, SDA) –10 µA
4-LEVEL LOGIC DC SPECIFICATIONS (APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
VLVL_H LEVEL-H input voltage Measured voltage at 4-level pin with external 1 kΩ to VIN VIN V
VLVL_F LEVEL-F default voltage Measured voltage 4-level pin at default 2/3 × VIN V
V LVL_R LEVEL-R input voltage Measured voltage at 4-level pin with external 20 kΩ to VSS 1/3 × VIN V
VLVL_L LEVEL-L input voltage Measured voltage at 4-level pin with external 1 kΩ to VSS 0 V
IIH Input high leakage current
(Vinput = VIN)		 4-levels (HOST_EQ0, MODE_SEL, SLEW_CTRL, SDI_VOD) 20 45 80 µA
SMBus mode: 4-levels (ADDR0, ADDR1) 20 45 80 µA
IIL Input low leakage current
(Vinput = GND)		 4-levels (HOST_EQ0, MODE_SEL, SLEW_CTRL, SDI_VOD) –160 –93 –40 µA
SMBus mode: 4-levels (ADDR0, ADDR1) –160 –93 –40 µA
RECEIVER SPECIFICATIONS (IN0±)
RIN0_TERM DC input differential termination Measured across IN0+ to IN0– 80 100 120 Ω
RLIN0_SDD11 Input differential return loss(1) SDD11, 10 MHz – 2.8 GHz –22 dB
SDD11, 2.8 GHz – 6 GHz –16 dB
SDD11, 6 GHz – 11.1 GHz –10 dB
RLIN0_SCD11 Differential to common-mode input conversion(1) SCD11, 10 MHz to 11.1 GHz –21 dB
VIN0_CM DC common-mode voltage Input common-mode voltage at IN0+ or IN0– to GND 2.06 V
CDON_IN0 Signal detect (default)
Assert ON threshold level for IN0±		 11.88 Gbps, EQ and PLL pathological pattern 20 mVp-p
CDOFF_IN0 Signal detect (default)
Deassert OFF threshold level for IN0±		 11.88 Gbps, EQ and PLL pathological pattern 18 mVp-p
DRIVER OUTPUT (SDI_OUT1+ AND SDI_OUT2+)
ROUT_TERM DC output single-ended termination SDI_OUT1+ and SDI_OUT1–,
SDI_OUT2+ and SDI_OUT2– to VIN		 63 75 87 Ω
VODCD_OUTP Output single-ended output voltage Measure AC signal at SDI_OUT1+ and SDI_OUT2+, with SDI_OUT1– and SDI_OUT2– AC terminated with 75 Ω
SDI_VOD = H		 840 mVp-p
SDI_VOD = F 720 800 880 mVp-p
SDI_VOD = R 880 mVp-p
SDI_VOD = L 760 mVp-p
VODCD_OUTN Output single-ended output voltage Measure AC signal at SDI_OUT1– and SDI_OUT2-, with SDI_OUT1+ and SDI_OUT2+ AC terminated with 75 Ω
SDI_VOD = H		 840 mVp-p
SDI_VOD = F 720 800 880 mVp-p
SDI_VOD = R 880 mVp-p
SDI_VOD = L 760 mVp-p
PRECD_OUTP Output pre-emphasis Output pre-emphasis boost amplitude at SDI_OUT1+ and SDI_OUT2+, programmed to maximum setting through register, measured at SDI_VOD = F 2 dB
PRECD_OUTN Output pre-emphasis Output pre-emphasis boost amplitude at SDI_OUT1– and SDI_OUT2–, programmed to maximum setting through register, measured at SDI_VOD = F 2 dB
tR_F_SDI Output rise and fall time (1) Measured with PRBS10 pattern, default VOD at 20% – 80% amplitude, default pre-emphasis enabled
11.88 Gbps		 34 42 ps
5.94 Gbps 36 43 ps
2.97 Gbps 59 67 ps
1.485 Gbps 60 73 ps
270 Mbps 400 550 700 ps
tR_F_DELTA Output rise and fall time mismatch(1) Measured with PRBS10 pattern, default VOD at 20% – 80% amplitude, default pre-emphasis enabled
11.88 Gbps		 3 18 ps
5.94 Gbps 2.7 12 ps
2.97 Gbps 0.8 11 ps
1.485 Gbps 0.8 12 ps
270 Mbps 72 150 ps
VOVERSHOOT Output overshoot or undershoot Measured with PRBS10 pattern, default VOD, default pre-emphasis enabled(2)
12G/6G/3G/HD/SD		 5%
VDC_OFFSET DC offset 12G/6G/3G/HD/SD ±0.2 V
VDC_WANDER DC wander 12G/6G/3G/HD/SD with EQ pathological pattern 20 mV
RLCD_S22 Output return loss at SDI_OUT1+ and SDI_OUT2+ reference to 75 Ω(1) S22, 5 MHz to 1.485 GHz –25 dB
S22, 1.485 GHz to 3 GHz –22 dB
S22, 3 GHz to 6 GHz –12 dB
S22, 6 GHz to 12 GHz –8 dB
DRIVER OUTPUT (OUT0±)
ROUT0_TERM DC output differential termination Measured across OUT0+ and OUT0– 80 100 120 Ω
VODOUT0 Output differential voltage at OUT0± Measured with 8T pattern
HOST_EQ0 = H		 410 mVp-p
HOST_EQ0 = F 485 560 620 mVp-p
HOST_EQ0 = R 635 mVp-p
HOST_EQ0 = L 810 mVp-p
VODOUT0_DE De-emphasized output differential voltage at OUT0± Measured with 8T pattern
HOST_EQ0 = H		 410 mVp-p
HOST_EQ0 = F 550 mVp-p
HOST_EQ0 = R 545 mVp-p
HOST_EQ0 = L 532 mVp-p
tR/tF Output rise and fall time Measured with 8T Pattern, 20% – 80% amplitude 45 ps
RLOUT0-SDD22 Output differential return loss(1) Measured with the device powered up and outputs a 10-MHz clock signal
SDD22, 10 MHz – 2.8 GHz		 –24 dB
SDD22, 2.8 GHz – 6 GHz –16 dB
SDD22, 6 GHz – 11.1 GHz –15 dB
RLOUT0-SCC22 Output common-mode return loss(1) Measured with the device powered up and outputs a 10-MHz clock signal.
SCC22, 10 MHz – 4.75 GHz		 –12 dB
SCC22, 4.75 GHz – 11.1 GHz –9 dB
VOUT0_CM AC common-mode voltage on OUT0±(1) Default setting, PRBS31, 11.88 Gbps 8 mV (rms)
OUTPUT JITTER
ADDJCD Additive jitter(1) Measured at SDI_OUT1+ and SDI_OUT2+, OUT0± disabled
PRBS10, 12G/6G/3G/HD/SD		 0.03 UI
(1) This parameter is measured with the LMH1297EVM (Evaluation board for LMH1208).
(2) VOVERSHOOT overshoot and undershoot maximum measurements are largely affected by the PCB layout and input test pattern. The maximum value specified in Electrical Characteristics for VOVERSHOOT is based on bench evaluation across temperature and supply voltages with the LMH1297EVM.
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