7.4.1.1 SMBus Read and Write Transaction

SMBus is a two-wire serial interface through which various system component chips can communicate with the master. Slave devices are identified by having a unique device address. The two-wire serial interface consists of SCL and SDA signals. SCL is a clock output from the master to all of the slave devices on the bus. SDA is a bidirectional data signal between the master and slave devices. The LMH1208 SMBus SCL and SDA signals are open-drain and require external pullup resistors.

Start and Stop:

The master generates Start and Stop patterns at the beginning and end of each transaction.

• Start: High-to-low transition (falling edge) of SDA while SCL is high.
• Start: High-to-low transition (falling edge) of SDA while SCL is high.

Figure 10. Start and Stop Conditions

The master generates nine clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle. The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is recorded when the device pulls SDA low, while a NACK is recorded if the line remains high.

Figure 11. Acknowledge (ACK)