7.4.2.2 SPI Write Transaction Format

For SPI writes, the R/W bit is 0'b. SPI write transactions are 17 bits per device, and the command is executed on the rising edge of SS_N. The SPI transaction always starts on the rising edge of the clock.

The signal timing for a SPI Write transaction is shown in Figure 2. The prime values on MISO (for example, A7') reflect the contents of the shift register from the previous SPI transaction and are listed as don’t care for the current transaction.

Figure 15. Signal Timing for a SPI Write Transaction