8.1.1 General Guidance for All Applications

The LMH1218 supports two modes of configuration: SPI Mode, and SMBus Mode. Once one of these two control mechanism is chosen, pay attention to the PCB layout for the high speed signals. SMPTE specifies the requirements for the Serial Digital Interface to transport digital video at SD, HD, 3Gb/s and higher data rates over coaxial cables. One of the requirements is meeting the required Return Loss. This requirement specifies how closely the port resembles 75-Ω impedance across a specified frequency band. The SMPTE specifications also defines the use of AC coupling capacitors for transporting uncompressed serial data streams with heavy low frequency content. This specification requires the use of a 4.7µF AC coupling capacitors to avoid low frequency DC wander. The 75-Ω signal is also required to meet certain rise/fall timing to facilitate highest eye opening for the receiving device. The LMH1218 built-in 75-Ω termination minimizes parasitic, improving overall signal integrity. Note: When the FPGA is not transmitting valid SMPTE data, the FPGA output should be muted (P=N).