ZHCSIC9D April   2016  – June 2018 LMH1219

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  4-Level Input Configuration Pins
      2. 7.3.2  Input Carrier Detect
      3. 7.3.3  -6 dB Splitter Mode Launch Amplitude for IN0
      4. 7.3.4  Continuous Time Linear Equalizer (CTLE)
        1. 7.3.4.1 Adaptive Cable Equalizer (IN0+)
        2. 7.3.4.2 Adaptive PCB Trace Equalizer (IN1±)
      5. 7.3.5  Input-Output Mux Selection
      6. 7.3.6  Clock and Data Recovery (CDR) Reclocker
      7. 7.3.7  Internal Eye Opening Monitor (EOM)
      8. 7.3.8  Output Function Control
      9. 7.3.9  Output Driver Amplitude and De-Emphasis Control
      10. 7.3.10 Status Indicators and Interrupts
        1. 7.3.10.1 LOCK_N (Lock Indicator)
        2. 7.3.10.2 CD_N (Carrier Detect)
        3. 7.3.10.3 INT_N (Interrupt)
      11. 7.3.11 Additional Programmability
        1. 7.3.11.1 Cable Length Indicator (CLI)
        2. 7.3.11.2 Digital MUTEREF
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transactions
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
          1. 7.4.2.1.1 SPI Write Transaction Format
          2. 7.4.2.1.2 SPI Read Transaction Format
        2. 7.4.2.2 SPI Daisy Chain
    5. 7.5 LMH1219 Register Map
      1. 7.5.1 Share Register Page
      2. 7.5.2 CTLE/CDR Register Page
      3. 7.5.3 CableEQ/Drivers Register Page
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for SMPTE and 10 GbE Applications
      2. 8.1.2 Optimizing Time to Adapt and Lock
      3. 8.1.3 LMH1219 and LMH0324 Compatibility
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detail Design Procedure
      3. 8.2.3 Recommended VOD and DEM Register Settings
      4. 8.2.4 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 修订历史记录

Changes from C Revision (October 2017) to D Revision

Changes from B Revision (February 2017) to C Revision

  • 添加封装图Go

Changes from A Revision (May 2016) to B Revision

  • Changed eq_en_bypass bit description from "Gain Stages 3 and 4" to "Gain Stages 2 and 3" Go
  • Changed bit location of IN1 Carrier Detect Power Down Control from Reg 0x13[5] to Reg 0x15[6] Go

Changes from * Revision (April 2016) to A Revision

  • Deleted min and max VOD_DE amplitude specification when VOD_DE = Level F Go
  • Changed typical VOD_DE amplitude specifications for Levels F, R, and L Go
  • Changed DEM value and DEM register settings in Table 5 to match correct VOD_DE pin logic levelsGo
  • Added new row for VOD = 5, DEM = 5 setting in Table 10Go
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