ZHCSIC9D April   2016  – June 2018 LMH1219

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  4-Level Input Configuration Pins
      2. 7.3.2  Input Carrier Detect
      3. 7.3.3  -6 dB Splitter Mode Launch Amplitude for IN0
      4. 7.3.4  Continuous Time Linear Equalizer (CTLE)
        1. 7.3.4.1 Adaptive Cable Equalizer (IN0+)
        2. 7.3.4.2 Adaptive PCB Trace Equalizer (IN1±)
      5. 7.3.5  Input-Output Mux Selection
      6. 7.3.6  Clock and Data Recovery (CDR) Reclocker
      7. 7.3.7  Internal Eye Opening Monitor (EOM)
      8. 7.3.8  Output Function Control
      9. 7.3.9  Output Driver Amplitude and De-Emphasis Control
      10. 7.3.10 Status Indicators and Interrupts
        1. 7.3.10.1 LOCK_N (Lock Indicator)
        2. 7.3.10.2 CD_N (Carrier Detect)
        3. 7.3.10.3 INT_N (Interrupt)
      11. 7.3.11 Additional Programmability
        1. 7.3.11.1 Cable Length Indicator (CLI)
        2. 7.3.11.2 Digital MUTEREF
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transactions
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
          1. 7.4.2.1.1 SPI Write Transaction Format
          2. 7.4.2.1.2 SPI Read Transaction Format
        2. 7.4.2.2 SPI Daisy Chain
    5. 7.5 LMH1219 Register Map
      1. 7.5.1 Share Register Page
      2. 7.5.2 CTLE/CDR Register Page
      3. 7.5.3 CableEQ/Drivers Register Page
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for SMPTE and 10 GbE Applications
      2. 8.1.2 Optimizing Time to Adapt and Lock
      3. 8.1.3 LMH1219 and LMH0324 Compatibility
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detail Design Procedure
      3. 8.2.3 Recommended VOD and DEM Register Settings
      4. 8.2.4 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Single Supply Mode(1) VIN, VDDIO, VDD_CDR to VSS 2.375 2.5 2.625 V
Dual Supply Mode(2)(3) VIN, VDD_LDO to VSS 1.71 1.8 1.89 V
VDD_CDR, VDDIO to VSS 2.375 2.5 2.625
VDDSMBUS SMBus: SDA, SCL Open Drain Termination Voltage 2.375 3.6 V
VIN0_LAUNCH Source Launch Amplitude before coaxial cable Normal mode 0.72 0.8 0.88 Vp-p
Splitter mode 0.36 0.4 0.44
VIN1_LAUNCH Source Differential Launch Amplitude before 5-inch board trace 300 850 mVp-p
before 20-inch board trace 650 1000
TJUNCTION Operating Junction Temperature 100 °C
TAMBIENT Ambient Temperature –40 25 85 °C
NTpsmax(4) Maximum Supply Noise Tolerance 50 Hz to 1 MHz, sinusoidal <20 mVp-p
1.1 MHz to 6 GHz, sinusoidal <10
(1) In Single Supply Mode, the VIN, VDDIO and VDD_CDR supplies are 2.5 V. The VDD_LDO is the 1.8 V LDO output of an internal LDO regulator, the VDD_LDO pin should not be connected to any external supply voltage.
(2) In Dual Supply Mode, the VIN and VDD_LDO are connected to a 1.8 V supply, while the VDD_CDR and VDDIO supplies are 2.5 V.
(3) In Dual Supply Mode, the VDDIO and VDD_CDR supply should be powered before or at the same time as VIN and VDD_LDO = 1.8 V.
(4) The sum of the DC supply voltage and AC supply noise should not exceed the recommended supply voltage range.
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