ZHCSKF4C March 2017 – October 2019 LMH1228
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 4-Level Input Pins and Thresholds
- 7.3.2 OUT0_SEL and SDI_OUT2_SEL Control
- 7.3.3 Input Signal Detect
- 7.3.4 Continuous Time Linear Equalizer (CTLE)
- 7.3.5 Clock and Data (CDR) Recovery
- 7.3.6 Internal Eye Opening Monitor (EOM)
- 7.3.7 Output Function Control
- 7.3.8 Output Driver Control
- 7.3.9 Status Indicators and Interrupts
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
8.2.1 Dual Cable Driver
The LMH1228 can be configured as a dual cable driver to route the same SDI output signal to multiple receivers. In this configuration, the LMH1228 adaptively equalizes 100-Ω SDI input data at IN0 and uses the dual cable drivers at SDI_OUT1 and SDI_OUT2 to drive out the SDI signal.
Figure 21 shows a typical application of an LMH1228 as a dual cable driver output. In this example, the LMH1219 Cable EQ with Integrated Reclocker provides an SDI input to the SDI FPGA. The FPGA then sends post-processed SDI data to the IN0 of the LMH1228, which drives the data on cable driver outputs SDI_OUT1 and SDI_OUT2.
Figure 21. LMH1228 Dual Cable Driver Application